Staff/Sr Staff Design Verification Engineer (HSI- High Speed Interfaces)

September 5, 2025

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Job Description

Description

Staff/Sr Staff Design Verification Engineer (HSI- High Speed Interfaces) page is loaded

Staff/Sr Staff Design Verification Engineer (HSI- High Speed Interfaces)

Apply locations Toronto time type Full time posted on Posted 30+ Days Ago job requisition id JR

The Opportunity

We’re looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

Staff / Sr Staff Design Verification Engineer

We value growth and collaboration in the Digital Design Verification team. We enjoy working together and take pride in supporting each other to deliver results. Our group is fun, dynamic, and social. Those who wish to pursue a career in semiconductors will find many opportunities on this team to learn new skills, be challenged, and take on responsibilities.

What you’ll do:

  • Review design specifications and devise verification plan
  • Build testbenches and analyze test failures to uncover design bugs
  • Take on opportunities to lead, plan, and coordinate tasks with team members
  • Perform behavioral modeling of analog circuits
  • Facilitate bit-matching of RTL design and MATLAB system models
  • Integrate 3rd party VIPs for compliance testing of standard protocols
  • Build releases of our design IP for customers
  • Support post-silicon validation and bring-up activities
  • Work closely with Design, Systems, Analog, FW, and PD teams for final verification closure
  • Contribute towards the continuous improvement of verification methodologies and processes.

What You’ll Need:

  • We are open to candidates with experience levels ranging from 5yrs to 15 yrs,
  • Constrained-random verification with Systemverilog and UVM
  • SerDes PHY, DSP, and Analog Mixed-signal verification experience
  • Knowledge in Ethernet and PCIe standards is desirable
  • Formal verification, and Power-aware UPF verification techniques
  • Tools/Languages – Systemverilog, UVM, Python, Perl, C/C++, GNU Make

We have a flexible work environment to support and help employees thrive in personal and professional capacities.

You’ll also be eligible for competitive benefits described as per below:

Health & Wellness

Our programs emphasize knowledge and prevention, helping you stay proactive and prepared to manage your health at every stage.