Design Verification Engineer
Job Description
Description
This range is provided by HCLTech. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range
CA$90,000.00/yr – CA$110,000.00/yr
3 days per week onsite at Markhem, ON
3 years of relevant skill experience in the main DV (design verification) skillsets would be system Verilog and UVM
Job Description
SV functional coverage, Assertions coding
Regressions, coverage analysis
Experience
Experience writing ASIC/SoC testplans
Expertise & hands-on experience in UVM methodologies using SV
Experience in developing TB components, including functional coverage implementation and assertion coding
Experience in Perl/Shell scripting
Seniority level
-
Seniority level
Mid-Senior level
Employment type
-
Employment type
Full-time
Job function
-
Job function
Information Technology
-
Industries
IT Services and IT Consulting
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Company
HCLTech
Location
Markham
Country
Canada
Salary
100.000
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